Your feedback has been sent to our team.
8 Ratings
Hours/Week
No grades found
— Students
Professor Williams is easily one of the best professors I've had at UVa. He's very good at conveying information and making sure that you understand the material. He's very enthusiastic about what he is teaching, and most importantly, he's knowledgeable about the subject. He responds to in-class questions very well, again making sure that you completely understand the topic at hand. I don't think I've had an easier time learning from a professor than with Williams.
The course itself I found to be very interesting an fun. You learn about the different aspects of the architecture and microarchitecture of different combinational and sequential components. Labs were helpful in understanding the material. The last few weeks of the course, you design components to build a working processor, and if you can get all of the parts to mesh together nicely, it's really satisfying.
Overall it's a worthwhile course (and a required one for CpEs), and I definitely recommend taking it with Williams if you can.
Professor Williams is one of the best professors I have every had. Not only is he a great lecturer, he is incredibly knowledgeable about the topic and he cares deeply about the students.
The class is not easy. There are not many super advanced topics, so the quizzes and exams are pretty okay. What gets you is the labs one week after another. They keep getting more and more difficult. Good luck on the final project too, barely anyone actually gets it to work.
Williams is one of those professors that you can tell has been teaching this course for long enough that he has the material down pat. He's a great lecturer and he's good about highlighting what he wants you to take away from each lecture. As long as you pay attention in class and take notes/read over the slides a few times you should be able to do pretty well on tests.
Each week you have a lab that generally consists of designing and testing a component in VHDL that will become part of a processor. As long as you put in the time each week you should be able to have it done by the due date. As others have said you want to make sure that you get each lab right and don't just BS it because at the end you have to combine all of your components and if you messed up something on week three it becomes a lot harder to find and fix in the last week.
Overall the material was interesting and it's nice to have some hardware design language experience under your belt.
Labs start off pretty easy, but pick up fast. Don't be fooled - this class is more difficult than it initially seems, also because exams (20 MC questions) are 50% of your grade, and my semester there were only 2 of them. TAs are helpful, and so is the professor; he's actually hilarious and has been teaching the course for a while. As far as enjoyment goes, I found the labs to be a little monotonous - understanding the content is not hard, but implementing your RISC-V pipeline can be tedious. Get checked off by TAs ASAP, or run the risk of completing it late.
Ronald Williams does not teach this class, his TA's do. He will not even accept your work if the TA's did not help, they are even responsible for checking you off every week and staying behind 2/3 of class (Williams lectures for the first 50 minutes of the 3 hour class and then leaves as the TA's handle everything else). Most of the TA's are undergraduate students but they are helpful. This class is only offered in the spring; Williams will fail a student without a second thought and does not return emails, even if there is proven trauma or catastrophe in your life as there was in mine this past semester. He failed me my 4th year (yes, the same semester COVID broke out) even when I had a job lined up. I finished the work remotely and primarily on my own but he refused to look at it because the TAs didn't help me with it. When I went to the TAs, they told me Professor Williams instructed them to send me back to him, only for him to say "too bad" there isn't enough time left en route to failing me. Like I said, I finished the work but he refused to look at it and failed me even after I passed the final. He is tenured so UVa gives him free reign - beware. To succeed, try to get ahead and don't leave ANYTHING up to him or his lack of integrity, let the TAs determine your status in the course.
Get us started by writing a question!
It looks like you've already submitted a answer for this question! If you'd like, you may edit your original response.
No course sections viewed yet.